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oz6933 07/20/00 oz6933-sf-1.7 page 1 copyright 2000 by o 2 micro all rights reserved acpi cardbus controller features ? acpi-pci bus power management interface specification rev 1.1 compliant ? supports onnow lan wakeup, onnow ring indicate, pci clkrun#, pme#, and cardbus cclkrun# ? compliant with pci specification v2.2, 2000 pc card standard 7.1 ? yenta? pci to pcmcia cardbus bridge register compatible ? exca (exchangeable card architecture) compatible registers mappable in memory and i/o space ? intel tm 82365sl pcic register compatible ? supports pcmcia_ata specification ? supports 5v/3.3v pc cards and 3.3v cardbus cards ? supports two pc card or cardbus slots with hot insertion and removal ? supports multiple fifos for pci/cardbus data transfer ? supports direct memory access for pc/pci and pci/way on pc card socket ? programmable interrupt protocol: pci, pci+isa, pci/way, or pc/pci interrupt signaling modes ? win?98 irq and pc-98/99 compliant ? supports parallel or serial interface for socket power control including devices from micrel and ti ? zoomed video support; zoomed video buffer enable pins ? d3 cold state pme# wakeup support ? 3.3vaux power support ? integrated pc 98/99 -subsystem vendor id support, with auto lock bit ? led activity pins ordering information oz6933t ? 208 pin tqfp OZ6933B ? 208 pin mini-bga general description the oz6933 is an acpi and pc98/99 logo certified, high performance, dual slot pc card controller with a synchron- ous 32-bit bus master/target pci interface. this pc card to pci bridge host controller is compliant with the 2000 pc card standard. this standard incorporates the new 32-bit cardbus while retaining the 16-bit pc card specification as defined by pcmcia release 2.1. cardbus is intended to support ?temporal? add-in functions on pc cards, such as memory cards, network interfaces, fax/modems and other wireless communication cards, etc. the high performance and capability of the cardbus interface will enable the new development of many new functions and applications. the oz6933 cardbus controller is compliant with the latest acpi-pci bus power management interface specification. it supports all four power states and the pme# function for maximum power savings and acpi compliance. additional compliance to onnow power management includes d3 cold state support, paving the way for low sleep state power consumption and minimized resume times. to allow host software to reduce power consumption further, the oz6933 provides a power-down mode in which internal clock distribution and the pc card socket clocks are stopped. an advanced cmos process is also used to minimize system power consumption. the oz6933 dual pcmcia socket supports two 3.3v/5v 8/16-bit pc card r2 cards or 32-bit cardbus r3 cards. the r2 card support is compatible with the intel 82365sl pcic controller, and the r3 card support is fully compliant with the 2000 pc card standard cardbus specification. the oz6933 is a stand alone device, which means that it does not require an additional buffer chip for the pc card socket interface. in addition, the oz6933 supports dynamic pc card hot insertion and removal, with auto configuration capabilities. the oz6933 is fully compliant with the 33mhz pci bus specification, v2.2. it supports a master device with intern- al cardbus direct data transfer. the oz6933 implements a fifo data buffer architecture between the pci bus and cardbus socket interface to enhance data transfers to cardbus devices. the bi-directional fifo buffer permits the oz6933 to accept data from a target bus (pci or cardbus interface) while simultaneously transferring data. this architecture not only speeds up data transfers but also prevents system deadlocks. the oz6933 is a pcmcia r2/cardbus controller, providing the most advanced design flexibility for pc cards that inter- face with advanced notebook designs.
oz6933 oz6933-sf-1.7 page 2 functional block diagram pci interface pci configuration/ function control registers pci configuration/ function control registers pci arbite r pci arbiter cardbu s fifo cardbus fifo data buffering power switch contro l power switch control interrup t interrupt subsystem 16- bit pc card machin e exca 8/16-bit pc card state machine cardbus pc card state machine and arbiter pc card interface socket a pc card interface powe r switc h power switch interface acpi/ onnow power management for pc99 exca 8/16 bit pc card state machine cardbus pc card state machine and arbiter socket b pc card interface
oz6933 oz6933-sf-1.7 page 3 system block diagram the following diagram is a typical system block diagram utilizing the oz6933 acpi cardbus controller with other related chipsets. cpu north bridge vga agp memory pci bus oz6933 cardbus controller pc card south bridge isa pc card
oz6933 oz6933-sf-1.7 page 4 pin diagram - 208 pin tqfp b _ i o w r # / c a d 1 5 b _ a 9 / c a d 1 4 b _ i o r d # / c a d 1 3 b _ a 1 1 / c a d 1 2 b _ v s 1 / c v s 1 b _ o e # / c a d 1 1 b _ c e 2 # / c a d 1 0 b _ a 1 0 / c a d 9 b _ d 1 5 / c a d 8 b _ c e 1 # / c c b e 0 # b _ v p p _ v c c b _ d 1 4 / r f u b _ d 7 / c a d 7 b _ s o c k e t _ v c c b _ d 1 3 / c a d 6 b _ d 6 / c a d 5 b _ d 1 2 / c a d 4 b _ d 5 / c a d 3 b _ d 1 1 / c a d 2 b _ d 4 / c a d 1 b _ c d 1 # / c c d 1 # b _ d 3 / c a d 0 c o r e _ v c c l e d _ o u t / s k t _ a c t i v i t y s c l k / a _ v c c 5 # s d a t a / b _ v c c 3 # 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 1 5 6 1 5 5 1 5 4 1 5 3 1 5 2 1 5 1 1 5 0 1 4 9 1 4 8 1 4 7 1 4 6 1 4 5 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 5 3 5 4 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 7 4 7 2 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 3 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 1 0 4 s l a t c h / b _ v c c _ 5 # c o r e _ g n d s p k r _ o u t # o 2 m i c r o , i n c . o z 6 9 3 3 a u x _ v c c a _ c d 2 # / c c d 2 # a _ w p / c c l k r u n # a _ d 1 0 / c a d 3 1 a _ d 2 / r f u a _ d 9 / c a d 3 0 a _ d 1 / c a d 2 9 a _ d 8 / c a d 2 8 a _ d 0 / c a d 2 7 a _ b v d 1 / s t s c h g g _ r s t # a _ a 0 / c a d 2 6 a _ v p p _ v c c a _ b v d 2 / c a u d i o a _ a 1 / c a d 2 5 a _ r e g # / c c b e 3 # a _ a 2 / c a d 2 4 a _ i n p a c k # / c r e q # a _ a 3 / c a d 2 3 a _ w a i t # / c s e r r # a _ a 4 / c a d 2 2 a _ r e s e t / c r e s e t # a _ a 5 / c a d 2 1 p c i _ c l k p c i _ g n t # p c i _ r e q # a d 3 1 a d 3 0 p c i _ v c c a d 2 9 a d 2 8 a d 2 7 a d 2 6 a d 2 5 a d 2 4 c / b e 3 # c o r e _ g n d i d s e l a d 2 3 a d 2 2 a d 2 1 a d 2 0 a d 1 9 p c i _ v c c a d 1 8 a d 1 7 a d 1 6 c / b e 2 # c o r e _ g n d f r a m e # c o r e _ g n d i r d y # t r d y # d e v s e l # s t o p # p e r r # s e r r # p a r c / b e 1 # p c i _ v c c a d 1 5 a d 1 4 a d 1 3 a d 1 2 a d 1 1 a d 1 0 c o r e _ g n d a d 9 a d 8 c / b e 0 # a d 7 a d 6 a d 5 a d 4 p c i _ v c c ad0 ad3 ad2 ad1 core_gnd lock# a_d3/cad0 a_socket_vcc a_cd1#/ccd1# a_d4/cad1 a_d11/cad2 a_d5/cad3 a_d12/cad4 a_d6/cad5 a_d13/cad6 a_d7/cad7 a_d14/rfu a_ce1#/ccbe0# a_d15/cad8 irq15/ring_out a_a10/cad9 a_ce2#/cad10 a_oe#/cad11 a_vs1/cvs1 a_a11/cad12 a_iord#/cad13 core_vcc a_a9/cad14 a_iowr/cad15 a_a8/ccbe1# a_a17/cad16 a_a13/cpar a_a18/rfu a_a14/cperr# irq3/vcc3# a_a19/cblock# a_we#/cgnt# a_a20/cstop# a_rdy_ireq#/cint# a_a21/cdevsel# a_a16/cclk a_a22/ctrdy# a_a15/cirdy# a_a23/cframe# a_a12/ccbe2# socket_vcc a_a24/cad17 a_a7/cad18 gnd a_a25/cad19 a_a6/cad20 a_vs2/cvs2 b_a8/ccbe1# b_a17/cad16 b_a13/cpar b_socket_vcc b_a18/rfu b_a14/cperr# irq12/pme# b_a19/cblock# b_we#/cgnt# b_a20/cstop# b_rdy_ireq#/cint# b_a21/cdevsel# b_a16/cclk b_a22/ctrdy# b_a15/cirdy# b_a23/cframe# b_a12/ccbe2# b_a24/cad17 b_a7/cad18 b_a25/cad19 gnd b_a6/cad20 b_vs2/cvs2 core_vcc b_a5/cad21 b_reset/creset# b_a4/cad22 b_wait#/cserr# b_a3/cad23 b_inpack#/creq# b_a2/cad224 b_reg#/cc_be3# b_a1/cad25 b_bvd2/caudio b_a0/cad26 b_bvd1/cstchg irq11/sktb_actv b_d0/cad27 b_d8/cad28 b_d1/cad29 b_d9/cad30 b_d2/rfu b_d10/cad31 b_socket_vcc b_wp/cclkrun# b_cd2#/ccd2# inta# irq4/intb# irq5/serirq irq7/sin#/b_vpp_pgm rst# irq14/clkrun# 1 9 0 1 9 1 1 9 2 1 9 3 1 9 4 1 9 5 1 9 6 1 9 7 1 9 8 1 9 9 2 0 0 2 0 1 2 0 2 2 0 3 2 0 4 2 0 5 2 0 6 1 8 7 1 8 9 1 7 5 1 7 6 1 7 7 1 7 8 1 7 9 1 8 0 1 8 1 1 8 2 1 8 3 1 8 4 1 8 5 1 8 6 1 8 8 1 6 5 1 6 6 2 0 8 2 0 7 1 7 1 1 6 8 1 6 9 1 7 0 1 7 2 1 7 3 1 7 4 1 6 7 1 5 8 1 5 9 1 6 0 1 6 1 1 5 7 1 6 2 1 6 3 1 6 4
oz6933 oz6933-sf-1.7 page 5 pin list bold text = normal default pin name pci bus interface pins pin number pin name description tqfp bga input type power rail drive ad[31:0] pci bus address input/data: these pins connect to pci bus signals ad[31:0]. a bus transaction consists of an address phase followed by one or more data phases. 4-5, 7-12, 16- 20, 22-24, 38- 43, 45-46, 48- 49, 51-56 e1, e2, f3, f1, g5, h6, g3, g2, h2, h1, j1, j2, j3, j6, k1, k2, m5, n2, n1, n3, n6, p1, p3, n5, p6, r2, r3, t1, w4, r6, u5, p7 ttl i/o 4 pci spec c/be[3:0]# pci bus command/byte enable: the command signaling and byte enables are multiplexed on the same pins. during the address phase of a transaction, c/be[3:0]# are interpreted as the bus commands. during the data phase, c/be[3:0]# are interpreted as byte enables. the byte enables are to be valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path are to carry meaningful data for the current data phase. 13, 25, 36, 47 g1, k3, m3, r1 ttl i/o 4 - frame# cycle frame: this input indicates to the oz6933 that a bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is de-asserted, the transaction is in its final phases. 27 k6 ttl i/o 4 - irdy# initiator ready: this input indicates the initiating agent ? s ability to complete the current data phase of the transaction. irdy# is used in conjunction with trdy#. 29 l1 ttl i/o 4 - trdy# target ready: this output indicates target agent ? s the oz6933 ? s ability to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. 30 l2 ttl i/o 4 pci spec stop# stop: this output indicates the current target is requesting the master to stop the current transaction. 32 l5 ttl i/o 4 pci spec idsel initialization device select: this input is used as chip select during configuration read and write transactions. this is a point-to-point signal. idsel can be used as a chip select during configuration read and write transactions. 15 h5 ttl i 4 - devsel# device select: this output is driven active low when the pci address is recognized as supported, thereby acting as the target for the current pci cycle. the target must respond before timeout occurs or the cycle will terminate. 31 l3 ttl i/o 4 pci spec perr# parity error: the output is driven active low when a data parity error is detected during a write phase. 33 l6 - to 4 pci spec
oz6933 oz6933-sf-1.7 page 6 pin number pin name description tqfp bga input type power rail drive serr# system error: this output is driven active low to indicate an address parity error. 34 m1 - to 4 pci spec par parity: this pin generates pci parity and ensures even parity across ad[31:0] and c/be[3:0]#. during the address phase, par is valid after one clock. with data phases, par is stable one clock after a write or read transaction. 35 m2 ttl i/o 4 pci spec pci_clk pci clock: this input provides timing for all transactions on the pci bus to and from the oz6933. all pci bus signals, except rst#, are sampled and driven on the rising edge of pci_clk. this input can be operated at frequencies from 0 to 33mhz. 1 e3 ttl i 4 - rst# device reset : this input is used to initialize all registers and internal logic to their reset states and place most oz6933 pins in a high-impedance state. 207 d1 ttl i 1 - ri_out ring indicate out : this pin is ring indicate when the following occurs while o 2 mode control b register (index 2eh) bit 7 is set to 1: 1) power control (index+02h) bit 7 set to 1 2) interrupt and general control (index+03h) bit 7 set to 1 3) pci o 2 micro control 2 (offset: d4h) bit x = 0 72 v9 - to 1 6ma clkrun# pci clock run request: this signal is used by the central resource to request permission to stop the pci clock or to slow it down, and the oz6933 responds accordingly. to enable the clkrun# signal, you need to enable exca register 3b bit[3:2]. 208 a4 ttl i/o 4 pci spec pme# power management event: a power management event is the process by which the oz6933 can request a change of its power consumption state. usually, a pme occurs during a request to change from a power saving state to the fully operational state. 163 b14 - to 1 6ma sktb_actv socket b activity: this signal indicates that there is any activity on the socket b read/write access. refer to pci configuration register 90h. 193 e8 - to 1 6ma inta# pci bus interrupt a: this output indicates a programmable interrupt request generated from any of a number of card actions. although there is no specific mapping requirement for connecting interrupt lines from the oz6933 to the system, a common use is to connect this pin to the system pci bus inta# signal. 203 b5 - to 4 pci spec
oz6933 oz6933-sf-1.7 page 7 pin number pin name description tqfp bga input type power rail drive intb# pci bus interrupt b: t his output indicates a programmable interrupt request generated from any of a number of card actions. although there is no specific mapping requirement for connecting interrupt lines from the oz6933 to the system, a common use is to connect this pin to the system pci bus intb# signal. 204 f6 - to 4 pci spec irqser/ sout#/ irq5 irqser/sout#/irq5: in pc/pci serial interrupt signaling mode, this pin is the serial interrupt output, sout#. in pc/way mode, this pin is the irq serializer pin to the interrupt controller. in the parallel isa mode, this pin is the isa irq5 205 c5 ttl i/o 4 pci spec irq7/sin#/ b_vpp_pgm irq7/sin#/b_vpp_pgm: in pc/pci serial input signaling mode, this pin is the serial interrupt input, sin#. in the parallel isa mode, this pin is the isa irq7. this pin also can be configured as parallel power control pin b_vpp_pgm 206 e6 ttl i/o 1 6ma gnt# grant: this signal indicates that access to the bus has been granted. 2 f5 ttl i 4 pci spec req# request: this signal indicates to the arbiter that the oz6933 requests use of the bus. 3 g6 n/a to 4 pci spec lock# pci lock#: this signal is used by a pci master to perform a locked transaction to a target memory. lock# is used to prevent more than one master from using a particular system resource. 58 v5 ttl i/o 4 pci spec pci_vcc pci bus vcc: these pins must be connected to a 3.3-volt power supply. the pci bus interface pin outputs listed in this table (table 2-1) will operate at the voltage applied to these pins, independent of the voltage applied to other oz6933 pin groups. 6, 21, 37, 50 f2, j5, m6, p5 - pwr - - pcmcia sockets interface pins socket a pin number --- socket b pin number pin number socket a socket b name 1 description 2 tqfp bga tqfp bga qty i/o pwr drive -reg#/ ccbe3# register access: during pcmcia memory cycles, this output chooses between attribute and common memory. during i/o cycles for non-dma transfers, this signal is active (low). during ata mode, this signal is always inactive. for dma cycles on the oz6933 to a dma-capable card, -reg is inactive during i/o cycles to indicate dack to the pcmcia card. cardbus command byte enable: in cardbus mode, this pin is the ccbe3#. 112 n15 188 f9 1 i/o 2 or 3 cardbus spec. a[25:24]/ cad[19, 17] pcmcia socket address 25:24 outputs. cardbus address/data: cardbus mode, these pins are the cad bits 19 and 17. 102, 99 u15, w15 176, 174 c11, a11 2 i/o 2 or 3 cardbus spec. a23/ cframe# pcmcia socket address 23 output. cardbus frame: in cardbus mode, this pin is the cframe# signal. 96 u14 172 b12 1 i/o 2 or 3 cardbus spec.
oz6933 oz6933-sf-1.7 page 8 pin number socket a socket b name 1 description 2 tqfp bga tqfp bga qty i/o pwr drive a22/ ctrdy# pcmcia socket address 22 output. cardbus target ready: in cardbus mode, this pin is the ctrdy# signal. 94 w14 170 a13 1 i/o-pu 2 or 3 cardbus spec. a21/ cdevsel# pcmcia socket address 21 output. cardbus device select: in cardbus mode, this pin is the cdevsel# signal. 92 u13 168 b13 1 i/o-pu 2 or 3 cardbus spec. a20/ cstop# pcmcia socket address 20 output. cardbus stop: in cardbus mode, this pin is the cstop# signal. 90 w13 166 c13 1 i/o-pu 2 or 3 cardbus spec. a19/ cblock# pcmcia socket address 19 output. cardbus lock: in cardbus mode, this signal is the cblock# signal used for locked transactions. 88 u12 164 a14 1 i/o-pu 2 or 3 cardbus spec. a18/ rfu pcmcia socket address 18 output. reserved: in cardbus mode, this pin is reserved for future use. 85 d11 161 c14 1 to 2 or 3 cardbus spec. a17/ cad16 pcmcia socket address 17 output. cardbus address/data: in cardbus mode, this pin is the cad bit 16. 83 u11 158 e14 1 i/o 2 or 3 cardbus spec. a16/ cclk# pcmcia socket address 16 output. cardbus clock: in cardbus mode, this pin supplies the clock to the inserted card. 93 v13 169 e12 1 i/o 2 or 3 cardbus spec. a15/ cirdy# pcmcia socket address 15 output. cardbus initiator ready: in cardbus mode, this pin is the cirdy# signal. 95 p13 171 c12 1 i/o-pu 2 or 3 cardbus spec. a14/ cperr# pcmcia socket address 14 output. cardbus parity error: cardbus mode, this pin is the cperr# signal. 86 v12 162 a15 1 i/o-pu 2 or 3 cardbus spec. a13/ cpar pcmcia socket address 13 output. cardbus parity:b in cardbus mode, this pin is the cpar signal. 84 r11 159 c15 1 i/o 2 or 3 cardbus spec. a12/ ccbe2# pcmcia socket address 12 output. cardbus command/byte enable: in cardbus mode, this pin is the ccbe2# signal. 97 v14 173 a12 1 i/o 2 or 3 cardbus spec. a[11:9]/ cad[12, 9, 14] pcmcia socket address 11:9 output. cardbus address/data: in cardbus mode, these pin are the cad bits 12, 9 and 14. 77, 73, 80 v10, u9, w11 153, 149, 155 f14, f18, f15 3 i/o 2 or 3 cardbus spec. a8/ ccbe1# pcmcia socket address 8 output. cardbus command/byte enable: in cardbus mode, this pin is the ccbe1# signal. 82 v11 157 a16 1 i/o 2 or 3 cardbus spec. a[7:0]/ cad[18, 20- 26] pcmcia socket address 7:0 outputs. cardbus address/data: in cardbus mode, these pins are the cad bits 18 and 20:26. 100, 103, 105, 107, 109, 111, 113, 116 p14, r14, t19, r17, n14, r19, p18, n17 175, 178, 181, 183, 185, 187, 189, 191 b11, f11, e10, f10, b9, e9, a8, b8 8 i/o 2 or 3 cardbus spec. d15/ cad8 pcmcia socket data/0 bit 15. cardbus address/data: in cardbus mode, this pin is the cad bit 8. 71 w9 148 f17 1 i/o 2 or 3 cardbus spec. d14/ rfu pcmcia socket data i/0 bit 14. reserved: in cardbus mode, this pin is reserved for future use. 69 v8 145 g17 1 i/o 2 or 3 2 ma
oz6933 oz6933-sf-1.7 page 9 pin number socket a socket b name 1 description 2 tqfp bga tqfp bga qty i/o pwr drive d[13:3]/ cad[6, 4, 2, 31, 30, 28, 7, 5, 3, 1, 0] pcmcia socket data i/0 bits 13:3. cardbus address/data: in cardbus mode, this pin is the cad bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0, respectively. 67, 65, 63, 124, 122, 120, 68, 66, 64, 62, 59 p8, v7, w6, l18, m19, m15, u8, w7, u7, p8, u6 142, 140, 138, 199, 197, 195, 144, 141, 139, 137, 135 h15, h17, h19, b6, a6, c7, g18, h14, h18, j14, j17 11 i/o 2 or 3 cardbus spec. d2/ rfu pcmcia socket data i/o bit 2. reserved: in cardbus mode, this pin is reserved for future use. 123 l19 198 f7 1 i/o 2 or 3 cardbus spec. d[1:0]/ cad[29,27] pcmcia socket data i/o bits 1:0. cardbus address/data: in cardbus mode, these pins are the cad bits 29 and 27, respectively. 121, 119 m18, m17 196, 194 b7, a7 2 i/o 2 or 3 cardbus spec. -oe/ cad11 output enable : this output goes active (low) to indicate a memory read from the pcmcia socket to the oz6933. cardbus address/data: in cardbus mode, this pin is the cad bit 11. 75 p9 151 g15 1 i/o 2 or 3 cardbus spec. -we/ cgnt# write enable : this output goes active (low) to indicate a memory write from the oz6933 to the pcmcia socket. cardbus grant: in cardbus mode, this pin is the cgnt# signal. 89 r12 165 e13 1 to 2 or 3 cardbus spec. -iord/ cad13 i/o read : this output goes active (low) for i/o reads from the socket to the oz6933. cardbus address/data: in cardbus mode, this pin is the cad bit 13. 78 u10 154 e17 1 i/o 2 or 3 cardbus spec. -iowr/ cad15 i/o write : this output goes active (low) for i/o writes from the oz6933 to the socket. cardbus address/data: in cardbus mode, this pin is the cad bit 15. 81 p10 156 d19 1 i/o 2 or 3 cardbus spec. wp/ -iois16/ cclkrun# write protect/ i/o is 16-bit : in memory card interface mode, this inputs is interpreted as the status of the write protect switch on the pcmcia card. in i/o card interface mode, this input indicates the size of the i/o data at the current address on the pcmcia card. cardbus clock run: in cardbus mode, this pin is the cclkrun# signal, which starts and stops the cardbus cclk. to enable the clkrun# signal, exca register 3bh/7bh bit[3:2] must be enabled. 125 l17 201 a5 1 i/o-pu 2 or 3 cardbus spec.
oz6933 oz6933-sf-1.7 page 10 pin number socket a socket b name 1 description 2 tqfp bga tqfp bga qty i/o pwr drive -inpack/ creq# input acknowledge : the -inpack function is not applicable in pci bus environments. however, for compatibility with other cirrus logic products, this pin should be connected to the pcmcia socket ? s -inpack pin. cardbus request: in cardbus mode, this pin is the creq# signal. 110 p17 186 c9 1 i-pu 2 or 3 cardbus spec. rdy/ -ireq/ cint# ready/interrupt request : in memory card interface mode, this input indicates to the oz6933 that the card is either ready or busy. in i/o card interface mode, this input indicates a card interrupt request. cardbus interrupt: in cardbus mode, this pin is the cint# signal. this signal is active-low and level-sensitive. 91 p12 167 f12 1 i-pu 2 or 3 cardbus spec. -wait/ cserr# wait : this input indicates a request by the card to the oz6933 to halt the cycle in progress until this signal is deactivated. cardbus system error: in cardbus mode, this pin is the cserr# signal. 108 r18 184 a9 1 i-pu 2 or 3 cardbus spec. cd[2:1]/ ccd[2:1]# card detect : these inputs indicate to the oz6933 that a card is in the socket. they are internally pulled high to the voltage of the auxvcc power pin. cardbus card detect: in cardbus mode, these inputs are used with cvs[2:1] to detect presence and type of card. 126, 61 l14, v6 202, 136 c6, j15 2 i-pu- schmitt 1 cardbus spec. -ce2/ cad10 card enable pin is driven low by the oz6933 during card access cycles to control byte/word card access. -ce1 enables even-numbered address bytes, and -ce2 enables odd-numbered address bytes. when configured for 8- bit cards, only -ce1 is active and a0 is used to indicate access of odd- or even- numbered bytes. cardbus address/data: in cardbus mode, this pin is the cad bit 10. 74 r9 150 e19 1 i/o 2 or 3 cardbus spec. -ce1/ ccbe0# card enable pin is driven low by the oz6933 during card access cycles to control byte/word card access. -ce1 enables even-numbered address bytes, and -ce2 enables odd-numbered address bytes. when configured for 8- bit cards, only -ce1 is active and a0 is used to indicate access of odd- or even- numbered bytes. cardbus command/byte enable: in cardbus mode, this pin is the ccbeo# signal. 70 w8 147 g14 1 i/o 2 or 3 cardbus spec. reset/ crst# card reset : this output is low for normal operation and goes high to reset the card. to prevent reset glitches to a card, this signal is high-impedance unless a card is seated in the socket, card power is applied, and the card ? s interface signals are enabled. cardbus reset: in cardbus mode, this pin is the crst# output. 106 p15 182 c10 1 to 2 or 3 cardbus spec.
oz6933 oz6933-sf-1.7 page 11 pin number socket a socket b name 1 description 2 tqfp bga tqfp bga qty i/o pwr drive bvd2/ -spkr/ -led/ caudio battery voltage detect 2/speaker/ led : in memory card interface mode, this input serves as the bvd2 (battery warning status) input. in i/o card interface mode, this input can be configured as a card ? s -spkr binary audio input. for ata or non-ata (sff-68) disk-drive support, this input can also be configured as a drive- status led input. cardbus audio: in cardbus mode, this pin is the caudio input. 114 m14 190 c8 1 i-pu 2 or 3 - bvd1/ -stschg/ -ri/ cstschg battery voltage detect 1/status change/ring indicate : in memory card interface mode, this input serves as the bvd1 (battery-dead status) input. in i/o card interface mode, this input is the -stschg input, which indicates to the oz6933 that the card ? s internal status has changed. if bit 7 of the interrupt and general control register is set to `1`, this pin serves as the ring indicate input for wakeup-on- ring system power management support. cardbus status change: in cardbus mode, this pin is the cstschg. this pin can be used to generate pme#. 118 n19 192 f8 1 i-pu 2 or 3 - vs2/ cvs2 voltage sense 2: this pin is used in conjunction with vs1 to determine the operating voltage of the card. this pin is internally pulled high to the voltage of the auxvcc power pin under the combined control of the external data write bits and the cd pull up control bits. this pin connects to pcmcia socket pin 57. cardbus voltage sense: in cardbus mode, these pins are the cvs2 pins. 104 w16 179 a10 1 i/o-pu 1 cb-spec vs1/ cvs1 voltage sense 1: this pin is used in conjunction with vs2 to determine the operating voltage of the card. this pin is internally pulled high to the voltage of the auxvcc power pin under the combined control of the external data write bits and the cd pull up control bits. this pin connects to pcmcia socket pin 43. cardbus voltage sense: in cardbus mode, these pins are the cvs1 pins. 76 w10 152 e18 1 i/o-pu 1 cb-spec socket_vcc connect these pins to the vcc supply of the socket (pins 17 and 51 of the respective pcmcia socket). these pins can be 0, 3.3, or 5 v, depending on card presence, card type, and system configuration. the socket interface outputs (listed in this table, table 2-2) will operate at the voltage applied to these pins, independent of the voltage applied to other oz6933 pin groups. 60, 198 r7, r13 200, 160, 143 e7, f13, g19 2, 3 pwr - - 1 to differentiate the sockets in the pin diagram, all socket- specific pins have either a_ or b_ prefixes to the pin names indic ated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2 when a socket is configured as an ata drive interface, socket interface pin functions change.
oz6933 oz6933-sf-1.7 page 12 power control and general interface pins pin number pin name description tqfp bga input type power rail drive spkr_out speaker output: this output can be used as a digital output to a speaker to allow a system to support pc card fax/modem/voice and audio sound output. this output is enabled by setting the socket ? s misc control 1 register bit 4 to ? 1 ? (for the socket whose speaker signal is to be directed from bvd2/- spkr/-led to this pin). 128 k19 ttl i/o 1 6ma led_out/ skta_actv led output/skta_actv: this output can be used as an led driver to indicate disk activity when a socket ? s bvd2/- spkr/-led pin has been programmed for led support. in the o2 mode(index 3b/7b bit 5) , this pin indicates the socket a activity. the socket b activity refers to pci configuration register offset 90h (mux control register) 133 j19 ttl i/o 1 6ma cpwrclk/ a_vcc5# card power clock: this input is used as a reference clock (10-100 khz, usually 32 khz) to control the serial interface of the socket power control chips. a_vcc5#: this active-low output controls the 5 -volt supply to the a socket ? s vcc pins. the active-low level of this output is mutually exclusive with that of a_vcc3#. 132 k14 ttl i/o 1 6ma cpwrdata/ b_vcc3# card power serial data: this pin serves as output data pin when used with the serial interface of texas instruments ? tps2206idf & micrel 2564 socket power control chip. b_vcc3#: this active-low output controls the 3.3-volt supply to the a socket ? s vcc pins. the active-low level of this output is mutually exclusive with that of b_vcc5#. 131 k15 ttl i/o 1 6ma cpwrlatc/ b_vcc5# card power serial latch: this pin serves as output latch pin when used with the serial interface of texas instruments ? tps2206idf & micrel 2564 socket power control chip. b_vcc5#: this active-low output controls the 5 -volt supply to the a socket ? s vcc pins. the active-low level of this output is mutually exclusive with that of b_vcc3#. 130 k17 n/a i/o 1 6ma
oz6933 oz6933-sf-1.7 page 13 pin number pin name description tqfp bga input type power rail drive irq3/ a_vcc3# a_vcc3#/irq3 : this active-low output controls of the 3.3-volt supply to the socket ? s vcc pins. the active-low level of this output is mutually exclusive with of vcc_5#. this mode active only in sktpwr parallel mode enabled. this pin can be irq3 in parallel irq mode. 87 w12 n/a to 1 6ma irq9/ a_vpp_vcc vpp_vcc/irq9: this active-high output controls the socket a vcc supply to the socket ? s vpp1 and vpp2 pins. the active-high level of this output is mutually exclusive with that of vpp_pgm. this mode active only in sktpwr parallel mode enabled this pin can be configured as irq9 in parallel irq mode. 115 p19 n/a to 1 6ma irq10/ b_vpp_vcc vpp_vcc/irq10: this active-high output controls the socket b vcc supply to the socket ? s vpp1 and vpp2 pins. the active-high level of this output is mutually exclusive with that of vpp_pgm. this mode active only in sktpwr parallel mode enabled. this pin can be configured as irq10 in parallel irq mode. 146 f19 n/a to 1 6ma g_rst# global_reset#: this signal can be connected to either pci reset or acpi reset depending on system implementation. if the d3 cold state is implemented, this signal should be connected to the acpi reset, otherwise, connect to pci reset. this signal can reset the pme content under the d3 cold state if aux_vcc is provided 117 n18 ttl i 1 - power, ground, and reserved pins pin number pin name description tqfp bga input type power rail drive aux_vcc this pin must be connected to the system ? s 3.3-volt supply. 127 l15 n/a pwr - - core_vcc this pin provides power to the core circuitry of the oz6933. it must be connected to a 3.3 power supply. 180, 134, 79 b10, j18, r10 n/a pwr - - gnd all oz6933 ground pins must be connected to system ground. 14, 26, 28, 44, 57, 101, 129, 177 h3, k5, k5, p2, w5, v15, k18, e11 n/a gnd - - legend i/o type description power rail source of output?s power i input pin 1 aux_vcc: outputs powered from aux_vcc i-pu input pin with internal pull-up 2 a_slot_vcc: outputs powered from the socket a o output 3 b_slot_vcc: outputs powered from the socket b od open-drain 4 pci_vcc: outputs powered from pci bus power supply to tri-state output 5 core_vcc: outputs powered from the core_vcc to-pu tri-state output with internal pull-up od-pu open-drain output with internal pull-up pw power pin
oz6933 oz6933-sf-1.7 page 14 package specifications 157 208 1 52 d d 1 e 1 e b e f f 104 53 156 105 oz6933 208-pin tqfp o 2 micro, inc. seating plane a a1 a2 gage plane b l b l1 sec: f-f 0.25 inches millimeters symbol min nom max min nom max a - - 0.063 - - 1.60 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 1.181 30.00 bsc. d 1 1.102 28.00 bsc. e 1.181 30.00 bsc. e 1 1.102 28.00 bsc. e 0.020 bsc. 0.50 bsc. l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 0.039 ref 1.00 ref 0 3.5 7 0 3.5 7
oz6933 oz6933-sf-1.7 page 15 208 pin ? bga 7. solder ball depopulation is allowed. depopulation is the omission of 5. primary datum z and seating plane are defined by the spherical 6. a1 corner must be identified by ink mark, metallized markings, identation or other feature of package body, lid or integral heatslug, on the top surface of the package. 8. ball pad a1 corner indicator (nc) solder ball reflow and parallel to primary datum z, the original solder ball 4. dimension "b" is measured at the maximum solder ball diameter after 1. dimensioning and tolerancing per asme y14.5m-1994. 3. "n" represents the maximum number of solder balls for matrix size diameter is 0.45 mm. balls from a full matrix (m1 or m2). crowns of the solder balls. notes: m1 and m2. 2. "e" represents the solder ball grid pitch.

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